One type of integrated circuit logic which uses bipolar transistors is called emitter-coupled logic (ECL). ECL logic circuitry has the advantages that it is very fast, and has high input resistance, low output resistance, and low noise generation. ECL signal levels, referenced to a power supply voltage terminal commonly labelled V.sub.CC, are approximately (V.sub.CC -V.sub.BE) for a logic high voltage, and (V.sub.CC -2V.sub.BE) for a logic low voltage, where V.sub.BE is the forward biased base-emitter diode voltage drop or a corresponding bipolar transistor. In order to provide the logic high voltage (V.sub.CC -V.sub.BE), however, an extra transistor is necessary. A similar type of logic using bipolar transistors known as current-mode logic (CML) eliminates the need for an extra transistor by providing a logic high voltage of V.sub.CC, and a logic low voltage of approximately (V.sub.CC -V.sub.BE). The output level is thus more constrained but in many cases the saving of a transistor is advantageous.
Metal oxide semiconductor (MOS) transistors are now commonly being fabricated in integrated circuits along with bipolar transistors. As a result, some logic circuits providing CML-level output signals are required to receive at least one input signal compatible with the MOS transistors in addition to receiving at least one CML-level input signal. Complementary metal oxide semiconductor (CMOS) signal levels differ from ECL and CML signal levels. A CMOS logic high voltage is approximately V.sub.CC, whereas a logic low voltage is approximately a second power supply voltage, commonly labelled "V.sub.SS ", which is negative with respect to V.sub.CC. However when CMOS levels are applied to a base of a bipolar transistor in a CML logic circuit, reliability problems can result because of the differences in logic levels. A large reverse bias which occurs if a CMOS logic low voltage (about V.sub.SS) is applied to the base of an input bipolar transistor while the emitter is held at or near a CML logic high voltage (V.sub.CC) is harmful to the operation of the input bipolar transistor. When a large reverse bias is applied across the base-emitter junction of a bipolar transistor, degradation occurs. Over time, the constant application of this large reverse bias may cause the input bipolar transistor to fail, resulting in a failure of the entire integrated circuit. Electronically, a large reverse bias on a PN junction causes hot carrier injection into the overlying oxide, resulting in poor junction performance. See, for example, "Hot-Carrier Degradation in Bipolar Transistor at 300 and 110 K--Effect on BiCMOS Inverter Performance", by Burnett and Hu in IEEE Transactions on Electron Devices, vol. 37, no. 4, April 1990, pp. 1171-1173. The amount of hot carrier injection is proportional to the time the reverse bias occurs. The size of the reverse bias is related to the mean life of the transistor, for given worst case conditions, by an inverse semilogarithmic relationship; as the reverse bias decreases linearly, mean life increases exponentially. At typical values for reverse bias, transistor mean life in a mixed CML-CMOS logic circuit may be unacceptably short.